Principles of Modern Digital Design
Parag K. Lala
Format: PDF / Kindle (mobi) / ePub
A major objective of this book is to fill the gap between traditional logic design principles and logic design/optimization techniques used in practice. Over the last two decades several techniques for computer-aided design and optimization of logic circuits have been developed. However, underlying theories of these techniques are inadequately covered or not covered at all in undergraduate text books. This book covers not only the "classical" material found in current text books but also selected materials that modern logic designers need to be familiar with.
form using (a þ b þ c) ¼ (a þ b) (a þ c) (a þ b) ¼ a þ bc (by Postulate 3) Theorem 11. (i) xy þ x¯z ¼ (x þ z) (x¯ þ y). (ii) (x þ y)(x¯ þ z) ¼ xz þ xy. Proof: (by Postulate 3) xy þ x z ¼ (xy þ x )(xy þ z) ¼ (x þ x )(y þ x )(x þ z)(y þ z) (by Postulate 3) ¼ 1 Á (x þ y)(x þ z)(y þ z) (by Postulate 5) ¼ (x þ y)(x þ z)(y þ z) ¼ (x þ y)(x þ z) (by Postulate 4) (by Theorem 9ii) Example 2.4 Let us show the application of Theorem 11 in changing the form of the following Boolean
map for a three-variable Boolean function. odd, the Karnaugh map is a 2(n21)/2 Â 2(nþ1)/2 rectangular array. Thus for a three-variable function, the Karnaugh map is a 2 Â 4 array is shown in Figure 3.5. Figure 3.6 shows the Karnaugh map for a four-variable Boolean function, which contains 16 squares. Boolean expressions may be plotted on Karnaugh maps if they are expressed in canonical form. For example, the following Boolean expression may be represented by the Karnaugh map shown in Figure 3.7.
larger number of cells on the map than would be possible otherwise. In other words, only those don’t cares that aid in the simplification of a function are taken into consideration. Example 3.4 Let us minimize the following Boolean function using a Karnaugh map: f (A, B, C, D) ¼ Sm(0, 1, 5, 7, 8, 9, 12, 14, 15) þ d(3, 11, 13) The Karnaugh map is shown in Figure 3.15. From this the minimized function is given by f (A, B, C; D) ¼ D þ AB þ B C Again, it is emphasized that while considering
only if Cx (cofactor of C with respect to x) is a tautology. Thus if Sa is a tautology then a is covered by S. This is illustrated by using the cover of the function considered in the previous section for the REDUCE operator: 01 01 11 C1 partially redundant 10 11 01 C2 01 11 10 C3 relatively essential relatively essential 11 01 01 C4 partially redundant If C1 is considered first, then S becomes fC1, C2, C3, C4g 2 fC1g; note that this function does not have a don’t care set. Thus S becomes
not commonly available as commercial parts. Figure 4.15a shows the proper connections of a JK flip-flop in order to operate as an SR latch. 166 FUNDAMENTALS OF SYNCHRONOUS SEQUENTIAL CIRCUITS FIGURE 4.13 (a) Logic symbol for JK flip-flop, (b) truth table, and (c) Karnaugh map for deriving characteristic equation. FIGURE 4.14 A JK flip-flop constructed from a D flip-flop. 4.4 FLIP-FLOPS 167 FIGURE 4.15 (a) JK flip-flop as an SR latch and (b) D flip-flop. A JK flip-flop can also operate