Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters
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Analog Circuit Design contains the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 18 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of: Smart Data Converters: Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology, Filters on Chip: Chaired by Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired by Prof. M. Steyaert, Catholic University Leuven, Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.
with (b) zero-compensation Given a first-order approximation of the OpAmp (considering the finite DC gain Av 1), then the real transfer function of an ideal integrator with ¨int D 1/Rint Cint angular frequency, can be written as: Hint;real .s/ D GE Hint;ideal .s/ Hlp .s/ D GE Tclk 1 s Rint Cint 1 C 2 s FLP (4.1) The real transfer function is therefore affected by a gain-error GE and by a phaseloss equivalent to having a high-frequency pole FLP : GE D 1 1C !int 2 GBW FLP D Cint Cint C
ftrim . 2. The component selection area and power overhead is not negligible for close to minimum size devices. To assess this, let’s look into a representative circuit, which can be used as a “fundamental unit of digital trimming”: a digitally controlled switch, plus a passive element (Rtrim or Ctrim ) (Fig. 5.9). The overhead of using this passive element as a trim component are the parasitics of the switch, which load the component under trim, consume area and power and diminish the effect of
+ latches Fig. 6.3 Thermometer-coded Coarse DAC The Thermometer-coded MSB section (Coarse-DAC) determines the overall performance with respect to linearity and most of the design effort was focused on that block. The architecture is shown in Fig. 6.3. Although the final layout was not done in a matrix-style layout but rather in a single-line layout, the cells are driven by row and column decoders as this turns out to be area efficient. Latches are placed at the input of the DAC, after the
high levels of either co-channel or adjacent channel interference depending on the channel allocations in a particular situation. This issue was investigated through a series of “live” channel measurements using off the shelf 2.45 GHz wireless transceivers. A total of 12 nodes were used, 6 on each body, and the path loss between each node in the mesh was determined 17 times a second. Figure 7.2 shows the two BANs. Details for the experimental setup can be found in . Wearing the jackets and
voltage limiter has been implemented to protect the circuitry. By switching the references of this block a high accuracy with a high speed could be combined with a low power consumption. The communication protocol requires a very stable clock oscillator. The presented clock achieves a 2.5% accuracy over temperature and supply variation by carefully designing the temperature coefficient of the bias current. The tag is currently in production and used in amongst others airplane part tracking